Thank you very much for joining us here today at Nine Dot Connects You’re in the right place If you are here for our monthly Webinar on practical aspects of signal integrity, this is part two This webinar has a lot to cover, so without further ado, I’m going to turn the comm over to Tom Cassidy Hello everyone and thank you for joining me for part two of the Nine Dot Connects webinar series on practical aspects of signal integrity My name is Tom Cassidy and I’m a senior engineer at Nine Dot Connects To provide a little information about myself I’ve been working in and around the field of electrical engineering for over 35 years. I’ve also dabbled in other areas such as mechanical engineering, applications programming, FPGA design and simulation of both mechanical and electrical systems and of course the field of signal integrity, which is the topic of this Webinar As I stated in part one, my intent for this webinar series is not to teach signal integrity per se, but to present a series of PCB layout design cases and show how we can apply signal integrity analysis to see what’s really going on and to determine any possible problems that might be occurring and of course we’ll probably pick up some signal integrity theory along the way As a review, here is a list of the design cases I presented in part one I essentially started off with the most basic PCB design I could think of, which was just two chips connected by a short straight trace, which I call the ideal route I then used the analysis results of this design as a baseline reference as I presented ever more complex PCB layout paradigms showing their effects on the integrity of the signal. I will review this simulation process shortly In part two we’ll be looking at some of the more advanced layout paradigms associated with high speed design and layout Here’s a list of the topics I intended to cover, but as I was preparing the presentation, I ended up with a lot more material than I thought I would have had and as a result I was unable to present all of these topics in the time allotted So my apologies to those who thought this would be the end of the series, but it looks like I will be doing a part three after all and to be honest, there’ll probably be a part four as well Here’s the list of what I will be presenting in part two although it is but a subset of my original topic list, it does include a bonus topic that answers a question I received after the first session as well as a little bit more signal integrity theory And here’s the wishlist of what I’d like to cover in part three I will finally finish off with the DDR3 design, exploring some of the routing issues that are associated with it I will then touch on power distribution networks, or PDN analysis, as well as maybe some of the electromagnetic compatibility topics Before we continue, I’d like to have you answer a polling question So what I would like to know is what you think of the lots of the topics I just listed. So are the topic is good, just the right amount Do we have not enough topics and you want more, or there’s way too much and you want me to just give you a break? So, okay, so that looks like, let me go ahead and give you the sharing It looks like a lot of people think it’s just about right. That’s good to hear, and some people even want more So great. Glad to hear it. Okay, so let me go ahead and continue As I mentioned earlier, I’d like to give a quick overview of the simulation process that I will be using throughout the Webinar I’ll use the baseline design from part one here as an example For each design case I will have one or more layouts which I’ve created in Altium Designer Here you see my first ideal routing case from part one consisting of two chips and a single straight trace in between them I will also generate stackups appropriate for the design case in question Since I’m mainly interested in demonstrating a particular point, I will often take creative license with my stackups in order to get the best setup at the time, ignoring the reality of actually having to fabricate the board Once I’ve gotten my PCB designed, I export it to ODB++ and import it into Cadence Power SI, using a variety of utility programs and scripts to make the job a little bit easier Cadence Power SI is a very powerful program that performs EM modeling based on the geometry and composition of the PCB using both 2D and 3D field solvers The end result of this simulation is a frequency domain behavioral model For this Webinar, we’ll be using a form known as S-parameters Here’s an example of the kind of S-parameter graph I’ll be using to present the

frequency domain behavior of my design cases Since this is a pretty important part of signal integrity analysis, I’m going to describe the S-parameter graph in a little more detail A frequency domain behavioral model is essentially a mathematical model of the PCB that allows us to determine the effects that the physical board will have on signals as they propagate from the transmitter to the receiver. S-parameters essentially show how the circuit will behave over a range of frequencies with the x axis representing this frequency range Here you see that I simulated from DC up to 20 gigahertz As I mentioned earlier. This is rather atypical of most designs, but it does provide more data that I can use as I compare different design cases The y axis of an S-parameter graph represents the amount of energy transmitted or reflected for a given frequency Thus it goes from zero to one, with one indicating 100% amplitude at that frequency The red line at the top represents the percentage of the signal passing through the circuit. As we see at a frequency of zero or DC, there is 100% transmission This makes sense since copper traces are pretty good at conducting DC current You can also see that as the frequency increases, there is more and more attenuation of the signal This indicates that for various reasons, higher frequency signals have a harder time getting through PCB traces The blue signal at the bottom represents the amount of the signal that is reflected back to the transmitter. This is a slightly harder concept to grasp, but essentially it is an indicator of the impedance of the trace along with any mismatches that might be present. Once again, we see at DC there is no reflection occurring, while at higher frequencies the reflections start coming and going This periodic nature of the reflections is an indicator of various resonant conditions along the trace Getting back to the simulation process, we can now use this frequency domain behavioral model to determine how the system behaves in the time domain. To do this, we use the Cadence System SI program This tool will use the S-parameter model of the PCB along with models of the actual components themselves in order to generate waveforms in the time domain Here we see the three blocks representing the three simulation objects, the FPGA controller, the DDR memory device, and the PCB model itself Each of these blocks has a mathematical model associated with it The PCB block of course has the S-parameters we generated from Power SI The active components utilize a model known as IBIS, which stands for Input Output Buffer Information Specification This is essentially a mathematical model of just the operation of the IO pins themselves rather than a complete model of the device itself Once I’ve entered these models into the System SI program and set up simulation parameters such as the clock rate, I’m able to generate different kinds of waveforms of my signals These waveforms represent the system behavior in the time domain and are in the form of both the traditional waveform diagram as well as something called an eye diagram. I will talk more about eye diagrams later Before I continue with my regularly scheduled program, I’d like to take a small diversion and present the bonus design case that I mentioned earlier This design case is intended to address a question that was asked after part one of the series The question related to my design case about vias and their effects on the impedance of a trace I had presented two design cases in which I enlarged the diameter of the via while keeping everything else the same The questioner took exception to my conclusion that the signal integrity of the design actually got worse when I increased the via diameter He based his question on the fact that according to this equation, the inductance of a via gets smaller as the diameter increases His reasoning is that since the inductance of the via was decreased, the signal integrity of the trace should have been improved This is actually a very good question because it brings up an important issue regarding the very concept of inductance and how it applies to the impedance of a signal. I’ll be addressing this concept more in a bit, but for now, let me see if I can answer the question itself Here are my two design cases again Design case 1a has a via with an eight mil hole and a 15 mil pad, which exactly matches the 15 mil trace width Case 1B has a via with a 20 mil drill and a 30 mill pad Right away we can safely assume that the signal integrity will change and probably get worse since we now have a mismatch between the impedance of the

trace and the impedance of the pads In addition by enlarging new via pads, we have effectively added a capacitor to the trace formed by the pads and the PCB dielectric itself. And yes as the questioner pointed out, we have also changed the inductance of the via itself So I fibbed a little when I claimed that the only change I made was to the diameter of the via. Since I wanted to simulate a real world situation, I do have to accept the fact that other factors will also change as well Here’s a slide showing the frequency domain simulation results of the larger via There is a large resonant peak at about four gigahertz due to the combined effect of all of the changes I mentioned above And here is a slide showing the comparison to the previous design with the smaller via. As you can see there is a rather dramatic change But remember we are looking at some pretty high frequencies, the large majority of designs we’ll only have to worry about frequencies less than about two gigahertz So my answer to the question is that by changing the via diameter, I didn’t just change the inductance, but I also changed a variety of other factors, all of which combined together and affect the overall impedance of the trace and thus affects the signal integrity of the design as well. And as we see, lower inductance does not necessarily have a direct correlation to lower impedance Rather if the impedance of the trace is a combination of a lot of different factors This example also illustrates the dangers of putting too much faith into equations that only provide approximations There are just too many things going on that can affect signal integrity and simulation must be used if you want to have more accuracy I know that the title of this Webinar is practical aspects of signal integrity, but I would like to take a small detour and talk a little bit about theory And what I’d like to talk about is inductance What is it really and why do we have to worry about it? There seems to be a lot of confusion surrounding the very concept of inductance, which is a shame because inductance is perhaps the single most important electrical property when it comes to signal integrity problems There are so many aspects to inductance that is hard to understand which one’s important A lot of the problems seems to stem from the fact that the term inductance is just too ambiguous and in fact does not really mean anything all by itself Rather more often than not, when using the word inductance, we are really talking about something that should more properly be termed partial self inductance The term partial comes about from the fact that we are not looking at the entire inductance of a circuit, but simply a small part of it. So why does this matter? In a nutshell, self inductance is essentially the ability of something to create a magnetic field And since magnetic fields are only generated by moving currents and all occurrence flow in a loop, it follows that you need to have a loop of current to fully define the inductance of a circuit And in fact this is the genesis of the term loop inductance which more accurately describes the property of inductance So if we go back to our equation for the estimated inductance of a via, we now understand that this equation should more properly be called the equation for the partial self inductance of the via. And in addition to being partial, it also relates to the inductance that is only inherent in the via by itself And thus the word self As we know it is possible to have mutual inductance between conductors as in the case when two traces are close together The magnetic field lines from one trace overlap the other trace effectively changing its magnetic field and thus changing its inductance This introduces yet another term, that of partial mutual inductance So while we can use an equation to estimate the partial self inductance of a via, for example, that value does not necessarily represent the actual inductance as applies to the entire circuit The presence of another current in the vicinity of the via might add some partial mutual inductance to the situation rendering the initial calculation incorrect I presented another example of this effect in part one when I examine the effects of trace spacing on the serpentine traces often used in length tuning If the legs of the serpentine are too close, their mutual inductance can change the overall inductance of the trace rendering the length tuning calculations incorrect as well There is actually another interesting effect due to mutual self inductance that I’d like to touch upon briefly, something known as the skin effect and its related term skin depth But to do this I’ll have to discuss inductance theory in a little more detail As I mentioned earlier, the property of inductance can be thought of as the ability to create a magnetic field based on the amount of current flow

A common way of denoting a magnetic field is by drawing rings around the line of current. The more rings that are present, the stronger the magnetic field and thus the greater inductance Obviously you have to choose a convention that relates to the number of rings you draw for a given amount of current, but as long as you are consistent in following this convention, using magnetic field rings is a good way of indicating the magnetic field intensity Another property of these rings is that they represent the direction of the magnetic field as well as its intensity They essentially act as vectors showing the direction as well as magnitude This implies that a combination of overlapping magnetic fields can be modeled by adding the vectors represented by the magnetic field rings To put it more simply, if two magnetic fields are present at a given point in space and the magnetic field lines surrounding that point are pointing in the same direction, the vectors add together and that point sees a stronger magnetic field Conversely, if the field line rings are in the opposite direction, then the magnetic field is weaker at that point Let’s apply this concept to three pieces of wire instead of the two we used to discuss partial mutual inductance Here the green dots represent cross sections of pieces of wire and the current is flowing in the same direction and all of the wires and is of the same amperage. Since all of the fields are in the same direction I’ll omit drawing the arrows for clarity. If I isolate wire one, we see that it is surrounded by two of its own field lines as well as an additional ring from wire two and thus has a total of three rings surrounding it. However, if I isolate wire two, the one in the middle, we see that it actually has a total of four rings around it, two from its own field and one from each of the other two wires So we can see that even though all three wires have the same current flowing through them, the central wire has a stronger magnetic field because the other two are helping it along. This is a very critical concept Let’s expand on this a bit and add in two more wires Starting to get a bit crowded, huh? But you can see how the same principle of additive magnetic field line rings applies. If I isolate wire two again, we see that it now has six rings around it while the other wires still only have three each Let’s take this one step further and add in even more wires around the outside We can see that wire two is getting a lot more rings around it and thus has a much stronger magnetic field compared to the other wires You’ll have to use your imagination a bit for this next part, since when I tried to draw all of the field lines, it got pretty messy But I think you can still see that if we added another ring of wires around the outside, their fields would also serve to increase the fields of the inner wires more than the outer wires. Now, the astute observer may be wondering just how, if the current flow increases the impedance, but the impedance reduces the current flow, why does this even work? Well, as Dr. Ian Malcolm says, nature finds a way It turns out to be a balancing act where just enough current flows to create just enough of a magnetic field to increase the impedance just enough to force the current to flow closer to the circumference of the wire If we keep taking things to the limit, mathematically speaking, and keep adding an infinite number of infinitely small wires, we end up with a solid piece of cylindrical copper, commonly known as a bigger piece of wire At DC and low frequencies the current is evenly distributed and we have the same inductance throughout the entire cross section Thus the current distributes itself evenly as well At higher AC frequencies, we showed that the central area has the strongest magnetic field and thus the highest inductance and the outer circumference has the lowest field strength and thus the lowest inductance. This is the genesis for the skin effect Since the impedance of an inductor gets worse at higher frequencies, it follows that the impedance of the center of the wire is higher than that of the outer edge While the actual distribution of the current density decays exponentially towards the center of the wire is more convenient to think about all of the current flowing in a cylinder and to define the dimensions of the cylinder based on the thickness of its wall This thickness is what is known as the skin depth and it makes it much easier to calculate the effective cross section of the conductor This skin depth is usually defined as the average penetration of the high frequency current, and is defined with this formula As I’m sure you can imagine, the same effect applies to any shape of conductor, although the geometry, the skin depth will of course be different, but conceptually the idea is the same for any shaped conductor including the rectangle of a PCB trace So how does this affect us directly? There are two main effects, increased trace resistance and increased loop inductance. Of the two, the loop inductance increase is small enough that it really doesn’t cause much

concern for us. The effects of increased resistance are worse Since the trace resistance is determined by the cross section of the copper and its bulk resistivity, and we’re essentially cutting down on the cross sectional area, the resistance will be going up. In fact, working out the math and or using a 2D field solver, we’ll show that the resistance can actually increase as much as up to 30 to 40% A more subtle aspect of this is that the trace resistance is now frequency dependent. That means the higher frequency signals will see higher resistance Note that this is a major contributor to signal distortion Higher frequencies are now attenuated more thus rounding off the signal edges This concludes my sidetrack into the theory of inductance For a more comprehensive explanation of what I’ve been talking about I highly recommend a book, “Signal and Power Integrity-Simplified” by Eric Bogatin Okay, and at this point I like to have another question, polling question, so I’d like to know why are you even attending this webinar? Are you just curious? Have no idea what signal integrity is all about? You heard about it but you might use it someday Are you familiar with it but just wanted to brush up, or are you having issues that you think you need to find a solution for? Let’s see, familiar with it, but just wanted to brush up seems to be the winner today Not a whole lot of people that are just curious. Okay, I’ll thank you for that Let’s go ahead and continue with the Webinar. Okay I think that’s enough theory Let’s get down to brass tacks and start looking at some real world situations For this design case, I’d like to look into the signal integrity issues that arise from the use of multiple reference planes. As I’m sure everyone is quite aware, it is pretty much impossible to route all of your signals on just one layer You must therefore use multiple layers and use vias to transition the traces between these layers. But I’d like to reiterate an extremely important concept In the world of high speed design, you’re never just routing a signal trace You are routing the signals, return current path at the same time This is important enough that I’ll say it another way Every high speed signal has two parts to the routing, the trace itself and the return current path Both of these parts have to be routed at the same time, even if the return path is actually going to be on a reference plane To expound upon this even more, I’m going to discuss two things about the return current path mirroring the trace Number one is the reason why this happens and number two is the reason why it’s important to let it happen Here’s a sketch that illustrates what I am talking about when I say the return current mirrors the signal trace. As you see, the return card in the reference plane is following the trace that is above it As we know, all current flow seeks the lowest impedance path At DC and low frequencies, resistance is the biggest player, and the current will look for the lowest resistance path. As frequencies increase, inductance becomes the dominant factor influencing impedance And it is the mutual inductance effect that is the dominant factor causing return currents to mirror the trace When two currents are flowing near each other but in the opposite direction, their magnetic field lines are also rotating in the opposite direction and thus the overlapping fields subtract This subtraction causes the effective inductance of each trace to be lower Applying this idea to the current flows in both the trace and a plane, we see that the area of greatest mutual inductance will be directly under the trace Therefore this will be the area of lowest impedance and the return current will try to flow in this area And here’s a picture of a simulation of this effect in action It shows the current density in a plane underneath a U shaped trace at various different frequencies. You can see that as the frequency increases, the current density around the and under the trace also increases I would also like to bring to your attention the range of frequencies being simulated here It is this 100 megahertz frequency value that is commonly considered the cutoff between low and high speed signals. However, as I explained in part one, in order for us to have sharp signal transitions, we need to use frequencies up to about two Gigahertz, so the return current for these high frequencies will obviously follow the signal trace very closely. Okay, so that is why the return current path mirrors the signal trace, but why is this important? There are actually plenty of reasons why you would want to have a clean return current path that can follow the trace path I covered this in more detail in part one,

but here’s the list of some of those benefits The end result of all of this is that you need to be very, very, very cognizant of the reference plane that is being used for your return current path, which brings us back to our original topic What happens when this reference plane actually changes To explore this topic, we are going to need a design that has multiple reference planes Therefore I have created a design case that is derived from my via example from part one as shown here. In this design, I switched traces from the top layer shown in red to the bottom layer shown in blue For this design I’ve added a second reference plane and here is the resulting stackup As you can see I made the central core 42 mils thick in order to better emulate a typical PCB which often has a thickness of about 62 mils The prepregs thicknesses are still the same in order to provide a controlled impedance trace of 40 ohms Here is a slide showing the relative thicknesses of the different dielectrics, and here is the 3D view of the same layout I’ve reduced the size of the plane so that we can see the other features, but you can still get the idea The top layer trace in red transitions to the bottom layer, trace in blue The top signal references the green plane and the bottom signal references the red plane Behind the transition to via we also see another via that is tying the two reference planes together. I’ll discuss this in more detailed later Here is the slide of the actual design that also includes the stitch via tying the two reference planes together. Okay, let’s simulate it and see what happens Here is the result of the frequency domain simulation. As you see, the S-parameter graph starts to get kind of messy at higher frequencies and there seemed to be some resident conditions that relate to the thickness of the core dielectric as well as the placement of the return vias, but all in all, there is nothing here that would really worry me Looking at the time domain analysis, we see that the signal is still pretty decent The red trace is the voltage of the FPGA pin and the blue trace is the voltage at the DRAM chip There is some slight delay as we would expect as well as a little ringing, but really not too bad at all Pretty much what we would expect with such a straightforward transition routing paradigm Unfortunately in many of today’s high density routing environments, it is sometimes just not possible to have ground planes as references for every high-speed signal layer Adding in layers just to provide reference planes can be prohibitive in some situations both in terms of cost and in the final board thickness, so how do we deal with this? As it turns out, from a high speed return current point of view, it does not really matter what the voltage potential of the reference plane actually is The main idea is that we have a solid low impedance layer of copper that allows the return current to mirror the placement of the signal trace as much as possible This means that it is possible to use a power plane as the return current path for high speed signals Obviously we can’t use a stitch via since these planes must remain electrically isolated If I remove the stitch via and we just leave the planes as they are with no connection, how would the signal integrity look? You would think it would be pretty bad, but let’s look at some real simulations to see I modified my previous design to remove the stitch via and I assign the bottom reference layer to VCC. However, I did keep the same stack up After simulation we get this S-parameter diagram. As you see, the higher frequencies are starting to get really messy and even within our two gigahertz range we’re seeing some bad reflection energy as seen here in the blue plot line. Surprisingly enough, looking at the time domain, we don’t really see much change The signal’s still look pretty good at least at this scale There is a very slight change and then ringing from the first design case, but it really doesn’t look like having uncoupled reference planes at different voltage potentials is having much of an effect in the time domain I have to give my usual caveat here This is a very clean layout with the intent to showcase a very specific design In the real world where we have a design with lots of more traces and components is very likely that we would see worse results in the time domain. However, I still think this is a very interesting result Let’s go back to the S-parameter graph and see how the two design cases compare in a more direct manner Here I’ve overlayed the first and second cases on the same graph The blue and red lines represent the second design case that we just did with uncoupled planes The light blue and green traces represent the coupled ground planes

As you see there are still some pretty dramatic differences The top traces representing the signal loss get much worse with the uncoupled planes and the bottom traces representing reflected energy also get worse So even though we didn’t see much of an effect in our time domain analysis, there’s definitely something bad happening in the frequency domain You will often see the suggestion that if you do need to use reference planes at different voltage levels, you will need to have a capacitor near the transition via in order to provide an AC current path between the two planes Let’s simulate this situation and see if the capacitor is really needed and if so, just what effect it has I’ve modified the design to include a capacitor near the transition via It is an 0402 sized capacitor and I use the model for a commonly available 0.1 microfarad capacitor. As it turns out, the actual capacitor value isn’t really all that important What really matters is the physical size of the capacitor, the smaller the case size, the lower the parasitic inductance that is associated with it I’ll examine this in a little more detail shortly, but for now let’s see how this design comes out in the simulation From within the Cadence Power SI program, I assigned a model for the capacitor and performed the simulation Since we’re mainly interested in the changes the capacitor created, I went ahead and overlaid the results of both this simulation and the previous one on the same graph Here the design with the capacitor is represented by the red and blue traces and the uncoupled planes by the green and light blue traces As we see there is some slight improvement, although at some frequencies it actually does even get worse So surprisingly enough adding in this kind of a stitch capacitor does not really make things much better. This doesn’t seem to make much sense Didn’t we provided better return current path and thus shouldn’t things have improved with respect to the signal integrity? Unfortunately, the real world is messing things up for us again While it is true that an ideal capacitor acts as is short at high frequencies, real world capacitors are not quite as well behaved As we see in this slide of the spice model of the capacitor a real world capacitor also has parasitic inductance associated with it and as we know, inductors act as open circuits at high frequencies This will tend to negate the benefits of the stitch capacitor as a current path So while the stitch capacitor does provide a return current path at relatively low frequencies, it loses disability at higher frequencies You would have to use a capacitor with a really low equivalent series inductance, or ESL, to get good stitching And this usually translates into spending more money Just out of curiosity, let’s revisit my earlier example in which we just had two uncoupled reference planes at different voltage potentials. I say they’re uncoupled, but this is really only true at DC and low frequencies Since we have two conductors separated by a dielectric, we essentially have a capacitor. And as we know, capacitors provide coupling at high frequencies So this might help explain why my uncoupled planes are not as bad as expected Inherited capacitor formed by their reference planes and the dielectric provide a return path for the higher frequency return currents My first example, I had a pretty thick dielectric between the reference planes about 42 mills, but that was just to have a thick PCB for my example What if we were to make this dielectric much thinner? We would in essence be increasing the capacitance by doing this and so it seems like this might work even better for a return path coupling I’ve created a copy of the previous design and the only change I made was to reduce the core dielectric thickness from 42 mils to five mils Everything else about the design is the same Here you can see the stackup that I use in the Cadence Power SI Once again, since I’m interested in seeing how things change, I’ve overlaid the simulation results of the thin dielectric with that of the thick dielectric As we see the difference is very dramatic across all frequency ranges Here are the red and blue lines are for the thin dielectric case and the light blue and green lines are for the thick dielectric case For the sake of completeness, I’ve also overlaid the plots of the stitch capacitor As we see the differences are just as dramatic but very similar to the uncoupled plane example. And here’s a slide that should be even more shocking I’ve overlaid the initial design case that had two ground planes connected by a stitch via and it is even worse than decoupled planes with a thin dielectric Here the red and blue lines are once again the thin dielectric and the light blue and green lines are for the stitched comment potential reference planes

Let’s close out this section with one more slide Comparing the uncoupled thin dielectric case with the ideal route of one signal layer and one reference plane layer As we see the general shapes of all of the curves are rather similar, which also helps give me a good feeling about the analysis. In fact, the transmitted power curves match almost exactly up to about two gigahertz other than a few small resonant conditions So when we have to transition our return current path between different reference planes, we have essentially three possible scenarios We can have these planes at the same potential and tied together with vias We can use stitching capacitors to connect planes that have different potentials or we can let the reference plane stay uncoupled but have a thin dielectric between them Based on the results of my thin dielectric example, I reached the somewhat startling conclusion that it is better to have a thin dielectric between your reference planes than it is to have the direct coupling between them and have them be widely spaced And coming in last place is the use of a stitching capacitor to provide an AC current path near the transition via Back when I first started doing PCB layouts, which was more years ago than I care to think about, the choice of routing on an inner versus outer layer was purely based on convenience. I just picked whatever layer had space for that trace A common routing paradigm was to put mostly horizontal traces on one layer and mostly vertical traces on another And they use of solid copper planes was merely a convenient way of connecting power and ground Just drop a via anywhere you needed to connect to a power or ground rail When the board consisted of all through hole components and vias, the route ability of each layer was pretty much the same anyway The use of surface mount technology parts, or SMT, changed the equation a bit by removing the need for through hole mountings, therefore somewhat increasing the routing area on the inner layers. However, over time things changed and I was forced to grow up and leave this simple innocence behind Once we begin to enter the realm of high speed signals and the need for greater signal integrity, your viewpoint on the geometry of the PCBs needs to change drastically as we’ve already seen in our previous design cases While the routing activity is actually very similar to that which I did in my youth, the thinking behind it has to be very different In the parlance of the times, this means using micro strips on the outer layers and striplines on the inner layers The defining characteristics of these types of traces does not necessarily have to do with what layer they’re on, but rather what layer or layers they are being referenced to A micro strip is defined as a trace that has only a single reference plane In order to obtain this kind of geometry, the micro strip is usually routed on an outer layer, thus ensuring that there is no copper above it I say “usually” because there is a relatively rare usage case in which the trace is actually buried in dielectric. This is known as an embedded micro strip, so it is technically not on the outer layer of the PCB, but it is on the top or bottom copper layer Conversely, a stripline is defined as a trace that is referencing two different planes Thus, by definition, a stripline must be on an inner layer There are two common variants of a stripline, symmetrical and asymmetrical These relate to the distances between the trace and the two reference planes, or in other words to the relative thicknesses of the dielectric layers Much like S-parameter graphs, this somewhat confusing terminology also comes to us from the world of microwave and RF engineering. In fact, the word stripline was actually once a proprietary brand name The two technologies were originally developed to provide microwave componentry, such as wave guides, antennas, filters, and so on, and such were greatly dependent on the geometric relationships between the copper and the dialectics As the same kinds of geometric relationships started transitioning to the world of high speed PCB design, the two terms came along with the baggage. But instead of referring to the microwave aspects, they’re now just mostly used as convenient terms for routing on the inner and outer layers. As it turns out, there are actually quite a few variations on a theme as we can see here All of these different flavors have specific uses along with different pros and cons for each one. For this Webinar, I’m only going to be discussing the three most common cases, the regular micro strip, the symmetric stripline, and the asymmetric stripline Okay, so let’s examine the effects of routing traces as micro strips versus striplines The primary first order effect has to do with the propagation speed of the

signal. As you may know, the signal propagation speed is determined by the properties of the material surrounding the trace, not the actual trace itself, and as we see here, the stripline is surrounded completely by dielectric material while our micro strip has air and maybe even soldermask and silkscreen on the top half of it What this means to us is that a signal will therefore propagate at a different speed on a stripline compared to that of a micro strip Here’s the first layout I’ll use in order to examine the various aspects of micro strips and striplines Since we’re mainly interested in looking at the overall timing aspects of the signals, I’ve created a design that has a long serpentine trace in order to give us some length to play with. In addition, I’ve expanded upon my four layer stackup, adding another signal layer in between the two reference planes While this ends up giving me an unrealistic five layer board, it will let me more easily compare and contrast just the effects caused by changing the routing layers I’ve also adjusted the dielectric thicknesses so that I end up with the same trace impedance as before, while still using the same trace width This is also pretty unrealistic Typically the trace width of a stripline is thinner than that of a micro strip for a given target impedance And in one last concession to improve clarity, I’ve put the components on the bottom of the PCB, and used vias to connect to both the stripline and the micro strip Even though I could have routed the micro strip on the same layer as the components, I did it this way so that both of the designs use vias, thus giving me as much commonality between the different design cases as possible It also matches the geometric diagrams I’ve been using with the micro strip on the top layer And here are the results of the 3D simulation in the frequency domain We can very much see the effects of having a longer trace length The higher frequencies are attenuated much quicker than before, as indicated by the slope of the red line And here are the results of the simulation in the time domain. As you see, I’ve managed to get some nice time delay between the signals The red trace is from the FPGA and the blue trace is at the DRAM chip This delay measures out to be about 1.38 nanoseconds I will now do the same simulations for the stripline case and here is the layout that I’ll use to do so. As you see, it looks just like the micro strip, but now the same trace is on an inner layer sandwiched between two ground planes Thus the only difference is that I moved the trace from the outer layer to the inner layer. Everything else remains the same including the trace impedance Here is the S-parameter graph I ended up with after doing the frequency domain simulation. While the overall shape is similar, we can see that it is actually much better behaved than the micro strip Here I’ve overlaid the micro strip and stripline graphs to give us a better comparison The red and blue lines are for the stripline and the light blue and green lines are for the micro strip We can see that the stripline has a much cleaner transmission curve shown here in red There are also a fewer resonant peaks and the reflected energy as shown in blue is also a much lower. And remember, since the only real difference is the routing layer, this gives us some indication about just how different the effects of stripline versus micro strip routing can be on the integrity of a signal After running the time domain simulation, we find almost exactly the same waveforms as before The signals are a little bit cleaner as a result of the better behavior of the stripline S-parameter graph, but otherwise they’d look almost exactly the same In fact they were so similar that I was worried that I had done something wrong in my simulations. After all, my premise was that the signal timing should be different between the two routing styles and I didn’t really see that here. However, it turns out that this was just a matter of scale When I zoom into a single transition, I do end up seeing the time differences that I was looking for. As we see here, the red trace is the signal at the FPGA The green trace is the micro strip signal at the DDR chip and the blue signal is for the stripline at the same pin Now we can see a definite difference in the time delay between the two routing types. The micro strip edge arrived sooner than the stripline, which matches the fact that the micro strip propagation time is faster With this routing case the difference is on the order of about 90 picoseconds Earlier in this section I briefly mentioned the reason for this propagation speed difference, but I’d like to look at this a little closer now since it’s a pretty important effect in the field of signal integrity analysis. As I said, the different propagation speeds have to do with the fact that the signal on a

micro strip trace sees a different effective dielectric constant than does the signal on the stripline Going back to my picture of a micro strip and a stripline cross section, we see that the micro strip has the PCB dielectric material only on the bottom half of the trace All of the stripline has the same material completely surrounding it Thus the electric field from the micro strip, will only see about half as much of this dielectric as does the electric field surrounding the stripline. In addition, the material on the top of the micro strip consists mostly of air, although as I mentioned, there is usually at least some amount of soldermask and also the possibility of some silkscreen The end result of this is that the signal on a micro strip sees a lower effective dielectric constant than that of the stripline A simulation tool like Cadence Power SI, will take all of these different materials into account when it calculates the effective dielectric constant You can see here that the specific materials are called out in the stackup And here are some of the actual values that Power SI uses For the dielectric constant of FR4, the material that makes up the PCB, Power SI is advanced enough to use a model that deals with the fact that the dielectric constant of FR4 is actually frequency dependent You can see these values at the right side of the table At lower frequencies it uses 4.24 and at 10 gigahertz the dielectric constant is down to 3.92 Except in cases where the signal integrity is absolutely essential, you will rarely use a symmetric stripline stackup More often than not, you will actually be using a variation of the asymmetric stripline From a steckup and routing perspective,this means that you will have a reference plane, two signal layers, and then another reference plane You may ask why would this be considered a stripline, if there is another signal layer on one side of the trace? In fact, the dielectric thicknesses and trace dimensions are calculated as if the other signals are not present. Thus, we really have two overlapping asymmetric stripline stackups The one big caveat to this routing paradigm is to keep your traces as orthogonal as possible. If the trace is run on top each other, you end up with something called a Broadside Coupled Stripline, and you will change your impedance calculations dramatically However, for the purposes of this Webinar, I’m just going to simulate a straightforward asymmetric stripline stackup and compare it to the symmetric results Here’s the graphic of the stackup I’ll be using showing the extra dielectric thickness below the signal layer Here are the frequency domain simulation results overlaid with the symmetrical case The red and blue lines are the asymmetric stripline results and the light blue and green are for the symmetrical case As you see the transmission energy as shown in red and green is almost exactly the same I should point out that the difference in the reflected energy in the blue lines is actually caused by the fact that I messed up the trace impedances by changing the dielectric thickness and not compensating for it in the trace width, so you can safely ignore this part of the result The main result can be derived from the transmission energy curves When we look at the results in the time domain simulation, we see that there really isn’t any appreciable difference in the signal delay This is shown by the almost exactly overlapping green and blue lines here representing both stripline routing paradigms So in conclusion, what have we learned from these design cases? We proved that signals propagate faster on micro strips than they do on striplines and by an amount that might end up being serious depending on the overall timing budget We also learned that the signal integrity effects of using asymmetric striplines is not that much different from that of symmetric striplines Thus there is no compelling case not to use them unless you are doing cutting edge high speed designs above two gigahertz and need to have the symmetric striplines A more subtle reason to use striplines rather than micro strips for your critical signals is the fact that for micro strip traces on the outer layers, the soldermask and even your silk screen layers change the effective impedance of the trace And since solder mask is not formed to as an exact tolerance as the other layers, it’s harder to predict its exact effect on the impedance So to be safe and sure, use striplines for the signals that need precise timing and signal integrity Although we were mainly focused on the timing effects of micro strip versus stripline, it turns out that there are also interesting effects on the amount of the far

end crosstalk caused by having different effective dielectric around the signal We’ll look more at this in part three Another aspect has to do with EMI radiation The propagation of signals on a stripline minimize the radiation of energy while micro strips tend to radiate In fact, as I mentioned earlier, micro strips were originally intended to act as microwave antennas and thus were designed intentionally radiate energy So if EMI or EMC is going to be a big issue in your design you might be better served routing your aggressive signals as striplines In this Webinar, I first did a review of my simulation methods and then answered a question from part one as well as injecting a little theory into the mix I then analyzed two additional design cases relating to the use of reference planes and comparing micro strip versus stripline routing schemes and here’s the list of remaining topics I’d like to cover Since I seem to always have more material than I planned, I’m expecting to have to do two more parts. In addition, please feel free to send in requests, if there is another topic you might want me to cover This concludes part two of my webinar series on practical aspects of signal integrity. Thank you all very much for attending We will now have one more polling question and then I will turn things back over to Paul for the final word and our Q and a session Okay , here is the last question We’d like to know how you would rate this presentation Was it good for what you needed? The information was good, but I didn’t do it very well. Delivery was okay, but the material was over your head. The literary was okay, but the material is not helpful or it just did meet your expectations at all Okay. I’ll go ahead and close it out, show you the results and I’m very gratified to see what it looks like I’m doing an okay job. Great, so I’m now going to turn this over to Paul All right. Thank you very much I’m going to just grab the screen here for just a moment. In the meantime, if you have any questions for Tom, please do put them in the questions segment of your GoToMeeting panel there He’s going to take a look at those while I talk to you for a few moments and then he will definitely have some time afterwards to answer some of those questions, and we will go past the hour for some of the Q&A We suspect that there are quite a bit of questions for you here So I’m going to, I bring up my screen here and well let’s talk a moment about Nine Dot Connects So you are here for a reason You either you put off signal integrity long enough and you realize that this has started to kind of bite you in the butt or you’have some signal integrity, you want it basically explained in logical steps and not just a bunch of mathematical formulas being thrown at you from like a textbook Or you may just want to determine what you might need for your design flow as well. As the old saying goes, there are those who have a signal integrity issues and those who don’t know that they have signal integrity issues at this point So what do we provide here at Nine Dot Connects? We do a lot of different things We do training, we do coaching, but what I want to focus on for a moment is our services So for all the services, the other things we do thermal analysis A few months ago we did a Webinar on this, so if you’re interested let us know We’ll be more than happy to get that Webinar link out to you But we do thermal analysis. We definitely do design for manufacturing This is a big issue that a lot of people are coming across, especially when transferring from prototype to production Library management has been a big topic that we’ve been addressing this past year, which we’ve done and when I talk about addressing, we’re addressing with a lot of our customers as they’re trying to get their libraries organized. And of course is signal integrity And that’s why Tom is putting a tremendous amount of time into this because we want to make sure that if you do have single integrity questions we are able to assist you with it. So we’re learning quite a bit And if you actually do want to learn the tool as well, whether it’s Cadence or Mentor, we have folks here at Nine Dot Connects who are versed in these tools over here And if you just want to bounce something off, if you want us to simply be a soundboard, we’re here to do that for you as well And lastly, if you can want an independent review of your board saying, Hey, we’ve looked at this but we just want a separate pair of eyes and to look at this and see what you’ve got there Certainly can do that as well So I don’t want to spend a whole lot of time here talking about Nine Dot Connects. I want to turn this back over to Tom, cause I’m pretty sure there’s some really good questions out there, but if you want more information, feel free to look at oursite, nonconnects.com that’s where we have all of our services listed [inaudible]